Non-linear high-frequency amplifier arrangement

ABSTRACT

A non-linear high-frequency amplifier arrangement suitable for generating power outputs &gt;1kW at frequencies of &gt;1MHz for plasma excitation is provided. The arrangement includes two LDMOS transistors each connected by their source connection to aground connection point, where the LDMOS transistors have the same design and are arranged in an assembly, a power transformer whose primary winding is connected to drain connections of the LDMOS transistors, a signal transformer whose secondary winding is connected by a first end to a gate connection of one LDMOS transistor and by a second end to a gate connection of the other LDMOS transistor, and a feedback path from the drain connection to the gate connection of each of the LDMOS transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of and claims priority under 35 U.S.C. §120 from U.S. Application Ser. No. 15/854,333 filed on Dec. 26, 2017,which is a continuation of PCT Application No. PCT/EP2016/065382 filedon Jun. 30, 2016, which claims priority from German Application No. DE10 2015 212 152.6, filed on Jun. 30, 2015. The entire contents of eachof these priority applications are incorporated herein by reference.

TECHNICAL FIELD

The invention relates to non-linear, high-frequency amplifierarrangements, e.g., for generating an output power of >1 kW atfrequencies of >1 MHz for plasma excitation.

BACKGROUND

Various amplifier arrangements are shown, for example, in the followingdocuments: US 2014/0167858 A1, US 2006/0158911 A1, U.S. Pat. No.6,157,258 A, US 2002/0149425 A1, U.S. Pat. No. 6,046,641 A.

Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors areknown, for example, from the following document: FreescaleSemiconductor, Technical Data, RF Power LDMOS Transistors, DocumentNumber: MRFE6VP61K25H Rev. 4.1, 3/2014.

Non-linear high-frequency amplifiers are used, inter alia, to generatepower suitable for implementing a plasma process. Laterally diffusedmetal oxide semiconductor (LDMOS) transistors, in particularextra-rugged LDMOS transistors, are suitable for use in amplifiers ofthis kind, in particular for applications having mismatched load, onaccount of the ruggedness of said transistors against fed-back energy.However, in cases of an extreme mismatch, even a transistor of this kindcould swing up and/or be quickly destroyed. This can lead toself-oscillation on account of excessively high amplification at aspecific load. Furthermore, an excessively rapid voltage increase mayswitch on a parasitic bipolar transistor in themetal-oxide-semiconductor field-effect transistor (MOSFET) structure andthereby destroy the transistor.

SUMMARY

One of the objects of the present invention is to provide ahigh-frequency amplifier arrangement that includes LDMOS transistors andthat is stable under a wide variety of different load conditions.

One aspect of the present invention features a non-linear high-frequency(HF) amplifier arrangement suitable for generating output power of >1 kWat frequencies of >1 MHz for plasma excitation, including: two LDMOStransistors, which are each connected to a ground connection point bytheir respective source terminals, the LDMOS transistors being embodiedalike and being arranged in a package; a power transformer, a primarywinding of which is connected to drain terminals of the LDMOStransistors; a signal transformer, a secondary winding of which isconnected at a first end to a gate terminal of one LDMOS transistor andat a second end to a gate terminal of the other LDMOS transistor, inparticular via a resistor; and a feedback path, in each case, from thedrain terminal to the gate terminal of each LDMOS transistor.

This measure (or configuration) makes it possible to prevent thehigh-frequency amplifier arrangement from undesirably becoming anoscillator when a positive feedback loop having a coupling factor of >1is closed. A loop of this kind can include: an input network, atransistor, an output network including a load, and/or a feedback. Forsmall-signal amplifiers, there are various criteria for determining thestability. In the case of a non-linear power amplifier, the criteria arenot applied and numerical simulation, if a suitable model is available,or experiments are relied on. In the case of a non-linear,high-frequency amplifier, two types of self-oscillation may occur.Self-oscillation may occur in the absence of a drive signal (eitherentirely autonomously or triggered by a drive signal and oscillationcontinuing after the drive signal is switched off) (first type ofself-oscillation). Furthermore, low-frequency signals can be observed,some of which only have a fraction of the working frequency, e.g., thedrive frequency of the transistors, and which only appear at a specificamplitude of the drive signal (second type of self-oscillation). Thefirst type of self-oscillation may involve large amounts of power, whichendangers the amplifier. In the second type of self-oscillation,contamination of the output signal occurs. Stabilization can be achievedaccording to the invention by introducing broadband feedback. This isdone by inserting a feedback path from the drain terminal to the gateterminal of an LDMOS transistor.

Broadband feedback can be achieved, for example, in that each feedbackpath includes a series circuit including a resistor and a capacitor. Inthis case, the resistor can have a resistance value in the range of, forexample, from 200 to 800 ohm, and the capacitor can have a capacitancein the range of, for example, from 0.01 to 5 nF.

Alternatively or additionally, the secondary winding of the signaltransformer can be connected at a first end to the gate terminal of oneLDMOS transistor by one or more resistive elements, and can be connectedat a second end to the gate terminal of the other LDMOS transistor byone or more resistive elements. Providing resistive elements produces“lossy gate wiring.” In this way, instabilities resulting fromself-oscillation can be effectively prevented.

In some embodiments, it is sufficient to use resistive elements having alow resistance value. For example, resistors having a resistance valuein the range of between 1 and 100 ohm can be used as resistive elements.Alternatively or additionally, the drain terminals of the LDMOStransistors can be connected to ground by at least one capacitor in eachcase. This measure reduces the impedance experienced by the drains athigh frequencies. As a result, undesired resonances are suppressed andthe risk of failure on account of excessive dV/dt is reduced.

The LDMOS transistors can be optimized for avalanche operation. Asurplus of energy produced by overvoltage is converted into heat. Aslong as the transistor does not overheat as a result of this, it willnot be destroyed. The gate-drain capacitance is also very low and thegate is shielded from the electrical field of the drain. As a result,the risk of rapid failure due to switching of the parasitic bipolartransistor is also greatly reduced. In unfavorable load conditions at ahigh drain current, however, failures can be observed in the amplifierfor smaller frequencies, e.g., 13.56 MHz. This can occur when harmonicsin the range of from 300 to 400 MHz make up a large proportion of thedrain voltage. One solution is to design the output network such that itis low-resistance at these frequencies and such that no high HF drainvoltage is generated. If this is not successful, however, it is helpfulto provide capacitors from the drains to ground for stabilizationpurposes. The connection of the drains to ground can be implemented atan extremely low terminal inductance.

Low terminal inductance may, for example, be achieved by connecting thecapacitors to ground by a plurality of parallel vias or bythrough-plating into a heat spreader of the LDMOS transistors. If ahigh-frequency amplifier is installed on a thin circuit board, theconnections of the capacitors to the ground plane may be implemented ina low-inductance manner by a plurality of parallel vias. In the case ofa multi-layered circuit board, however, this is difficult. In this case,the low-inductance connection can be achieved by through-plating intothe heat spreader of the transistor. The heat spreader is a metal platethat includes the assembly of LDMOS transistors. As a result, heatgenerated by the transistors can be distributed over a large surfacearea.

The likelihood of failure of the high-frequency amplifier arrangementcan be further reduced by providing a circuit board that lies flat on ametal cooling plate and that is connected to the cooling plate, whichcan be connected to ground, via a plurality of ground connections. Forexample, the assembly can be arranged on the circuit board. Heat cantherefore be conducted away from the assembly including the LDMOStransistors particularly well. Overheating of the transistors can thusbe largely prevented.

Another aspect of the present invention features methods of protecting ahigh-frequency amplifier arrangement according to the inventionsdescribed herein. In these methods, the high-frequency amplifierarrangement is operated as a non-linear amplifier arrangement in anormal mode. A set power is defined as a power supposed (or expected) tobe output by the high-frequency amplifier arrangement in the normalmode. When the set power is reduced by more than 50%, the high-frequencyamplifier arrangement is operated in a linear mode.

A load having a high quality factor feeds some of the stored energy backinto the amplifier after the high-frequency amplifier arrangement hasbeen switched off. Since the LDMOS transistors in this case conduct noor only very little quiescent current, a high-quality oscillatingcircuit, including the drain capacitor, an output network, and the load,is formed. There is a risk, here, of a parasitic bipolar transistorbeing switched and the LDMOS transistors thus being destroyed. Thecountermeasure according to the invention provides for a high-frequencypower output by the high-frequency amplifier arrangement to be switchedoff slowly. This can be achieved by operating the high-frequencyamplifier arrangement in a linear mode for a specific period of time.

In this case, the high-frequency amplifier arrangement can be operatedin the linear mode over at least two cycles of the output high-frequencypower. The LDMOS transistors operate inefficiently during this time. Asa result, the fed-back power can be safely converted into heat.

The high-frequency amplifier arrangement can be operated in the linearmode for at least 100 ns. This ensures that the high-frequency amplifierarrangement is switched off without being destroyed.

In the normal mode, the voltage levels of the drive signals for thegates of the LDMOS transistors can be selected such that the transistorsare operated at least temporarily in a saturation mode when switched on.In the linear mode, the voltage levels of the drive signals can beselected such that the transistors are not operated in the saturationmode. Therefore, the LDMOS transistors can be set to operate in thesaturation mode (e.g., a non-linear amplifier mode) or in anon-saturation mode (e.g., a linear mode) based on the voltage levels ofthe drive signals. If, for example, the high-frequency amplifier isintended to be switched off, e.g., the set power drops to zero, atransition into a linear mode can first be effected to protect thehigh-frequency amplifier arrangement.

Further features and advantages of the invention can be found in thefollowing description of embodiments of the invention, with reference tothe drawings, which show details essential to the invention, and in theclaims. The different features may each be implemented in isolation ortogether in any desired combinations in variants of the invention.

DESCRIPTION OF DRAWINGS

Embodiments of the invention are shown in the schematic drawings andexplained in greater detail in the following description.

In the drawings:

FIG. 1 shows a high-frequency amplifier arrangement according to theinvention.

FIG. 2A shows voltage curves of gate voltages and drain voltages ofLDMOS transistors when a set power is rapidly reduced.

FIG. 2B shows corresponding voltage curves when a set power is rapidlyreduced, but the high-frequency amplifier arrangement is still beingoperated in linear mode.

FIG. 3A shows graphs obtained when no capacitors are used between drainand ground.

FIG. 3B shows graphs obtained when capacitors are used between drain andground.

DETAILED DESCRIPTION

FIG. 1 shows a first embodiment of a high-frequency amplifierarrangement 1. The high-frequency amplifier arrangement 1 includes acircuit board 2 on which a package 3 is arranged. The package 3 includestwo LDMOS transistors S1, S2, which are embodied alike and are eachconnected to a ground connection point 5 by their respective sourceterminals.

To stabilize the high-frequency amplifier arrangement 1, which can beoperated in a non-linear manner, feedback paths 34, 35 are provided fromthe drain terminals of the LDMOS transistors S1, S2 to the gateterminals 15, 17. The feedback paths 34, 35 each include a seriescircuit having a resistor 36, 37 and a capacitor 38, 39.

The LDMOS transistors S1, S2 are each connected, by the drain terminalsthereof, to an end of a primary winding 6 of a power transformer 7,which is part of an output network. The secondary winding 4 of the powertransformer 7 is connected to ground 8 and also connected to ahigh-frequency output 9. A high-frequency power can be output throughthe high-frequency output 9, e.g., to a load.

The drain terminals of the LDMOS transistors S1, S2 are in each caseconnected to ground via a capacitor 32, 33. The connection is achievedby through-plating into a heat spreader of the LDMOS transistors S1, S2.

The high-frequency amplifier arrangement 1 further includes a signaltransformer 10, which includes a primary winding 11 that is connected toa high-frequency input 12. A supply power can be provided to thehigh-frequency amplifier arrangement 1 through the high-frequency input12. A set power is a power that is supposed to be output or generated bythe high-frequency amplifier arrangement 1 in a normal mode. Thesecondary winding 13 of the signal transformer 10 is connected to thegate terminal 15 of the LDMOS transistor S1 by a resistive element 14,e.g., a resistor. The secondary winding 13 is also connected to the gateterminal 17 of the LDMOS transistor S2 by a resistive element 16, e.g.,a resistor. The resistive elements 14, 16 and the secondary winding 13are therefore connected in series. Just like the power transformer 7,the signal transformer 10 is also arranged on the circuit board 2.

The gate terminals 15, 17 are connected, by resistors 22, 23, to acapacitor 30, which is in turn connected to ground 27. A DC voltagesource is connected to the terminal 31.

The circuit board 2 lies flat on a cooling plate 25, which can also beconnected to ground 26. In particular, the circuit board 2 is connectedto the cooling plate 25 by a plurality of ground connections 8, 27. Theground connection 5 is a ground connection point for transferring heatfrom LDMOS transistors S1, S2 to the cooling plate 25.

FIG. 2A shows a drain voltage curve 100 of the first LDMOS transistor S1and the drain voltage curve 101 of the second LDMOS transistor S2. Thegate voltage, by which the LDMOS transistors are driven, is indicated byreference numeral 102. Voltage peaks are indicated by a circle 103 andoccur in the drain voltage when the set power is reduced abruptly, inparticular when the high-frequency amplifier arrangement is switched offwithout changing to a linear amplifier mode after being switched off.Said voltage peaks should be avoided.

FIG. 2B shows the corresponding voltages 100, 101, 102 when, duringsudden reduction of the set power, there is a transition from anon-linear amplifier mode into a linear amplifier mode. It can be seenin this case that the voltage peaks do not arise in the drain voltages100, 101, as a result of which the LDMOS transistors are protected.

FIG. 3A shows, on the left-hand side, the differential mode impedance110 and, on the right-hand side, the common mode impedance 111 of thematching network (as seen from the drains) when no capacitors areprovided between drain and ground.

FIG. 3B shows, on the left-hand side, the differential mode impedance112 and, on the right-hand side, the common mode impedance 113 of thematching network (as seen from the drains) when corresponding capacitors32, 33 are used.

Other Embodiments

A number of embodiments of the invention have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the invention.Accordingly, other embodiments are within the scope of the followingclaims.

What is claimed is:
 1. A high-frequency amplifier arrangement for generating an output power of >1 kW at frequencies of >1 MHz for plasma excitation, the high-frequency amplifier arrangement comprising: a. first and second Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors, wherein each is connected to a ground connection point by their respective source terminals, and wherein the LDMOS transistors are embodied alike and are arranged in a package; b. a power transformer, a primary winding of which is connected to drain terminals of the LDMOS transistors; c. a signal transformer, a secondary winding of which is connected at a first end to a gate terminal of the first LDMOS transistor and at a second end to a gate terminal of the second LDMOS transistor; and d. a first feedback path from the drain terminal of the first LDMOS transistor to the gate terminal of the first LDMOS transistor and a second feedback path from the drain terminal of the second LDMOS transistor to the gate terminal of the second LDMOS transistor.
 2. The high-frequency amplifier arrangement of claim 1, wherein each of the first and second feedback paths comprises a respective series circuit including a respective resistor and a respective capacitor.
 3. The high-frequency amplifier arrangement of claim 2, wherein each of the respective resistors has a resistance value in a range from 200 ohm to 600 ohm, and each of the respective capacitors has a capacitance in a range from 0.5 nF to 5.0 nF.
 4. The high-frequency amplifier arrangement of claim 1, wherein the secondary winding of the signal transformer is connected at the first end to the gate terminal of the first LDMOS transistor by one or more first resistive elements and is connected at the second end to the gate terminal of the second LDMOS transistor by one or more second resistive elements, such that a lossy gate circuit is produced.
 5. The high-frequency amplifier arrangement of claim 4, wherein each of the resistive elements is configured as a resistor having a resistance value in a range from 1 ohm to 100 ohm.
 6. The high-frequency amplifier arrangement of claim 1, wherein the drain terminals of the LDMOS transistors are respectively connected to ground by at least one capacitor.
 7. The high-frequency amplifier arrangement of claim 6, wherein the capacitors are connected to ground by one of a plurality of parallel vias and through-plating into a heat spreader of the LDMOS transistors.
 8. The high-frequency amplifier arrangement of claim 1, further comprising a circuit board that lies flat on a metal cooling plate and is connected to the cooling plate.
 9. The high-frequency amplifier arrangement of claim 8, wherein the circuit board is connected to the metal cooling plate by a plurality of ground connections, and the metal cooling plate is connected to ground.
 10. The high-frequency amplifier arrangement of claim 8, wherein the package is arranged on the circuit board.
 11. The high-frequency amplifier arrangement of claim 1, wherein a primary winding of the signal transformer is connected to a high-frequency input, and a secondary winding of the power transformer is connected to a high-frequency output. 